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TDA9210
150 MHz PIXEL VIDEO CONTROLLER FOR MONITORS
PRELIMINARY DATA
FEATURE
s s s s
s s
s s
s
s s s
s s s
150 MHZ PIXEL RATE 2.7 ns RISE AND FALL TIME I2C BUS CONTROLLED GREY SCALE TRACKING VERSUS BRIGHTNESS OSD MIXING NEGATIVE FEED-BACK FOR DC COUPLING APPLICATION BEAM CURRENT ATTENUATION (ABL) PEDESTRAL CLAMPING ON OUTPUT STAGE POSSIBILITY OF LIGHT OR DARK GREY OSD BACKGROUND OSD INDEPENDENT CONTRAST CONTROL ADJUSTABLE BANDWIDTH INPUT BLACK LEVEL CLAMPING WITH BUILT-IN CLAMPING PULSE STAND-BY MODE 5 V TO 8 V POWER SUPPLY SYNC CLIPPING FUNCTION (SOG)
DIP20 (Plastic Package) ORDER CODE: TDA9210
DESCRIPTION The TDA9210 is an I2C Bus controlled RGB preamplifier designed for Monitor applications, able to mix the RGB signals coming from any OSD device. The usual Contrast, Brightness, Drive and Cut-Off Controls are provided. In addition, it includes the following features: - OSD contrast, - Bandwidth adjustment, - Grey background, - Internal back porch clamping pulse generator.
The RGB incoming signals are amplified and shaped to drive any commonly used video amplifiers without intermediate follower stages. Even though encapsulated in a 24-pin package only, this IC allows any kind of CRT Cathode coupling : - AC coupling with DC restore, - DC coupling with Feed-back from Cathodes, - DC coupling with Cut-Off controls of the Video amplifier (ST Amplifiers TDA9533/9530). As for any ST Video pre-amplifier, the TDA9210 is able to drive a real load without any external interface. One of the main advantages of ST devices is their ability to sink and source currents while most of the devices from our competitors have problems to sink large currents. These driving capabilities combined with an original output stage structure suppress any static current on the output pins and therefore reduce dramatically the power dissipation of the device. Extensive integration combined with high performance and advanced features make the TDA9210 one of the best choice for any CRT Monitor in the 14" to 17" range. Perfectly matched with the ST Video Amplifiers TDA9535/36, these 2 products offer a complete solution for high performance and cost-optimized Video Board Application.
Version 3.1
March 2000 1/19
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1
TDA9210
1 - PIN CONNECTIONS
IN1 ABL IN2
GNDL
1 2 3 4
20 19
IN3 GNDA
5
6 7 8 9 10
18 17 16 15
14 13 12 11
BLK HSYNC or BPCP OUT1 VCCP OUT2 GNDP OUT3 SDA SCL FBLK
VCCA
OSD1 OSD2 OSD3
2 - PIN DESCRIPTION
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol IN1 ABL IN2 GNDL IN3 GNDA VCCA OSD1 OSD2 OSD3 FBLK SCL SDA OUT3 GNDP OUT2 VCCP OUT1 HSYNC/BPCP BLK Description Red Video Input ABL Input Green Video Input Logic Ground Blue Video Input Analog Ground Analog VCC (5V) Red OSD Input Green OSD Input Blue OSD Input Fast Blanking SCL SDA Blue Video Output Power Ground Green Video Output Power VCC (5 V to 8 V) Red Video Output HSYNC/BPCP Blanking Input
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TDA9210
3 - BLOCK DIAGRAM
BLK FBLK 11 Output Clamp Pulse (OCL) Drive Output Stage 18 OUT1 VCCP 17
TDA9210
VREF IN1 1 Clamp
20
Contrast
IN2 3
Green Channel
16 OUT2
IN3 5 ABL 2 BPCP Contrast/8bit
Blue Channel
14 OUT3
Brightness Drive 8bits 3x8bits Latches I2C Bus Decoder D/A
Cut-off 8bits
15 GNDP
GNDL
4
IC OSD Cont. 4bits
Output DC Level 4bits
GNDA 6 VCCA 7
VREF 19 HSYNC or BPCP 13 12 SDA SCL 8 OSD1 9 OSD2 10 OSD3
See Figure 8 for complete BPCP and OCL generation diagram
4 - FUNCTIONAL DESCRIPTION
4.1 - RGB Input The three RGB inputs have to be supplied through coupling capacitors (100 nF). The maximum input peak-to-peak video amplitude is 1 V. The input stage includes a clamping function. The clamp uses the input serial capacitor as a "memory capacitor". To avoid a discharge of the serial capacitor during the line (due to leakage current), the input voltage is referenced to the ground. The clamp is gated by an internally generated "Back Porch Clamping Pulse" (BPCP). Register 8 allows to choose the way to generate this BPCP (see Figure 1). When bit 0 is set to 0, the BPCP is synchronized on the trailing or leading edge of HSYNC (Pin 19) (bit 1 = 0: trailing edge, bit 1 = 1: leading edge).
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TDA9210
Additionally, the IC automatically works with either positive or negative HSYNC pulses. - When bit 0 is set to 1, BPCP is synchronized on the leading edge of the blanking pulse BLK (Pin 20). One can use a positive or negative blanking pulse by programming bit 0 in Register 9 (See I 2C Table 3). - BPCP width can be adjusted with bit 2 and 3 (see Register 8, I2C table 2). - If the application already provides the Back Porch Clamping Pulse, bit 4 must be set to 1 (providing a direct connection between Pin 19 and internal BPCP). 4.2 - Synchro Clipping Function This function is available on channel 2 (Green Channel). When using the Sync On Green (SOG) (Synchro pulse included in the green channel inFigure 1.
R8b0=0 and R8b1=0 HSYNC/BPCP (Pin19)
put) the synchro clipping function must be activated (bit 7 set to 1 in register 9) in order to keep the right green output levels and avoid unbalanced colours. 4.3 - Blanking Input The Blanking pin (FBLK) is TTL compatible. The Blanking pulse can be: - positive or negative - line or Composite-type (but not Frame-type). 4.4 - Contrast Adjustment (8 bits) The contrast adjustment is made by controlling simultaneously the gain of the three internal amplifiers through the I2C bus interface. Register 1 allows the adjustment in a range of 48 dB.
Internal BPCP R8b0=0 and R8b1=1 HSYNC/BPCP (Pin19) Internal BPCP
R8b0=1 BLK (Pin20) Internal BPCP R8b4 =1 HSYNC/BPCP (Pin19) Internal BPCP
4.5 - ABL Control The TDA9210 includes an ABL (automatic beam limitation) input to attenuate the RGB Video signals depending on the beam intensity.
The operating range is 2 V (from 3 V to 1 V). A typical 15 dB maximum attenuation is applied to the output signal whatever the contrast adjustment is. (See Figure 2 ). When the ABL feature is not used, the ABL input (Pin 2) must be connected to a 5 V supply voltage.
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TDA9210
Figure 2.
0 -2 -4 -6 -8 -10 -12 -14 -16 0 Attenuation (dB)
VABL (V) 1 2 3 4 5
4.6 - Brightness Adjustment (8 bits) Brightness adjustment is controlled by the I2C Bus via Register 2. It consists of adding the same DC voltage to the three RGB signals, after contrast adjustment. When the blanking pulse equals 0, the DC voltage is set to a value which can be adjusted between 0 and 2V with 8mV steps (see Figure 3). The DC output level is forced to the "Infra Black" level (VDC) when the blanking pulse is equal to 1. 4.7 - Drive Adjustment (3 x 8 bits) In order to adjust the white balance, the TDA9210 offers the possibility of adjusting separately the overall gain of each channel thanks to the I2C bus (Registers 3, 4 and 5). The very large drive adjustment range (48 dB) allows different standards or custom color temperatures. It can also be used to adjust the output voltages at the optimum amplitude to drive the CRT drivers, keeping the whole contrast control for the enduser only. The drive adjustment is located after the Contrast, Brightness and OSD switch blocks, so it does not affect the white balance setting when the BRT is adjusted. It also operates on the OSD portion of the signal. 4.8 - OSD Inputs The TDA9210 allows to mix the OSD signals into the RGB main picture. The four pins dedicated to this function are the following: - Three TTL RGB inputs (Pins 8, 9, 10) connected to the three outputs of the corresponding OSD processor. - One TTL fast blanking input (Pin 11) also connected to the FBLK output of the OSD processor. When a high level is present on the FBLK, the IC acts as follows:
- The three main picture RGB input signals (IN1, IN2, IN3) are internally switched to the internal input clamp reference voltage. - The three output signals are set to the voltage corresponding to the three OSD input logic states (0 or 1). (See Figure 3). If the OSD input is at low level, the output and brightness voltages (VBRT) are equal. If the OSD input is at high level, the output voltage is VOSD, where V OSD = VBRT + OSD and OSD is an I2C bus-controlled voltage. OSD varies between 0 V to 4.9 V by 320 mV steps via Register 7 (4 bits). The same variation is applied simultaneously to the three channels providing the OSD contrast. The grey color can be obtained on output signals when: - OSD1 = 1, OSD2 = 0 and OSD3 = 1, - A special bit (bit 5 or 6) in Register 9 is set to 1. If R9b5 is set to 1, light grey is obtained on output. If R9b6 is set to 1, dark grey is obtained on output. In the case where R9b5 and R9b6 are set to 0, the normal operation is provided on output signals. 4.9 - Output Stage The overall waveforms of the output signal are shown in Figure 3 and Figure 4. The three output stages, which are large bandwidth output amplifiers, are able to deliver up to 4.4 VPP for 0.7 V PP on input. When a high level is applied on the BLK input (Pin 20), the three outputs are forced to "Infra Black" level (VDC) thanks to a sample and hold circuit (described below). The black level (which is the output voltage outside the blanking pulse with minimum brightness and no Video input signals) is 400 mV higher than VDC. The brightness level (VBRT) is then obtained by programming register 2 (see I2C table 1). The sample and hold circuit is used to control the "Infra Black" level in the range of 0.5 V to 2.5 V via Register 6 (in case of AC coupling) or Registers 10, 11, 12 (in case of DC coupling) . This sampling occurs during an internal pulse (OCL) generated inside the blanking pulse window. Refer to "CRT cathode coupling" part for further details.
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TDA9210
Functioning with 5 V Power VCC To simplify the application, it is possible to supply the power VCC with 5 V (instead of 8 V nominal) at the expense of output swing voltage. Functioning without Blanking Pulse If no blanking pulse is applied to the TDA9210, the internal BPCP can be connected to the sample Figure 3. Waveforms VOUT, BRT, CONT, OSD
and hold circuit (Register 8, bit 7 = 1 and BLK pin grounded) so that the output DC level is still controlled by I2C. To ensure the device correct behavior in the worst possible conditions, the Brightness Register must be set to 0.
HSYNC BPCP BLK Video IN FBLK OSD IN
V
(4) CONT (5) V OSD (3) VBRT (2) V BLACK VDC (1)
VOUT1 , VOUT2 , VOUT3 CONT BRT 0.4V fixed
OSD
Notes : 1. VDC 2. VBLACK 3. VBRT 4. VCONT 5. VOSD
= = = = =
0.5 to 2.5V V DC + 0.4V V BLACK + BRT (with BRT = 0 to 2V) V BRT + CONT = k x Video IN (CONT = 4.4VPP max. for VIN = 0.7V PP) V BRT + OSD (OSD max. = 4.9VPP , OSD min = 0VPP)
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TDA9210
Figure 4. Waveforms (Drive adjustment)
HSYNC
BPCP BLK Video IN BFLK OSD IN VOUT1, VOUT2, VOUT3
VCONT V OSD VBRT
VBLACK VDC Two examples of drive adjustment (1)
Note : 1.Drive adjustment modifies the following voltages : VCONT, VBRT and V OSD. Drive adjustment doesn't modify the following voltages : VDC and VBLACK.
4.10 - Bandwidth Adjustment A new feature: Bandwidth adjustment, has been implemented on the TDA9210. This function has several advantages: - Depending on the external capacitive load and on the peak-to-peak output voltage, the bandwidth can be adjusted to avoid any slew-rate phenomenon. - The preamp bandwidth can be adjusted in order to reduce electromagnetic radiation, since it is possible to slow down the signal rise/fall time at the CRT driver input without too much affecting the rise/fall time at the CRT driver output. - It is possible to optimize the ratio of the frequency response versus the CRT driver power consumption for any kind of chassis, as the preamp bandwidth adjustment also allows the adjustment of the rise/fall time on the cathode (through the CRT driver).
- In still picture mode, when a high Video swing voltage is of greater interest than rise/fall time, bandwidth adjustment is used to avoid any slewrate phenomenon at the CRT driver output and to meet electromagnetic radiation requirements. 4.11 - CRT Cathode Coupling (Figure 5) The TDA9210 is designed to be used in DC coupling mode, enabling to build a powerful video system on a small PCB Board and giving a substantial cost saving compared with any other solution available on the market. The preamplifier outputs control directly the cut-off levels. The output DC level (VDC) is adjusted independently for each channel from 0.5 V to 2.5 V via registers 10, 11 and 12. In DC coupling mode, bit 2 must be set to 1 and bit3 to 0 in Register 9.
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TDA9210
Figure 5. DC Coupling
TDA 9210
Pins 14-16-18 CRT Driver CRT
OUTPUT 1,2,3 DC LEVEL 0.5V to 2.5V (8bits)
4.12 - Stand-by Mode The TDA9210 has a stand-by mode. As soon as the VCC power (Pin 17) gets lower than 3V (typ.), the device is set in stand-by mode whatever the voltage on analog VCCA (Pin 7) is. The analog blocks are internally switched-off while the logic parts (I2C bus, power-on reset) are still supplied. In stand-by mode, the power consumption is below 20 mW. 4.13 - Serial Interface The 2-wire serial interface is an I2C interface. The slave address of TDA9210 is DC hex.
A6 1 A5 1 A4 0 A3 1 A2 1 A1 1 A0 0 W 0
In order to write data into the TDA9210, after the "start" message, the MCU must send the following data (see Figure 6): - the I2C address slave byte with a low level for the R/W bit, - the byte to the internal register address where the MCU wants to write data, - the data. All bytes are sent with MSB bit first. The transfer of written data is ended with a "stop" message. When transmitting several data, the register addresses and data can be written with no need to repeat the start and slave addresses. 4.14 - Power-on Reset A power-on reset function is implemented on the TDA9210 so that the I2C registers have a determined status after power-on. The Power-on reset threshold for a rising supply on VCCA (Pin 7) is 3.8 V (typ.) and 3.2V when the VCC decreases.
The host MCU can write into the TDA9210 registers. Read mode is not available.
Figure 6. I2C Write Operation
SCL SDA Start I2C Slave Address W A7 ACK A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Stop
Register Address
Data Byte
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TDA9210
5 - ABSOLUTE MAXIMUM RATINGS
Symbol VCCA Max. VCCP Max. Vin Max. VI Max. Tstg Toper Parameter Supply Voltage on Analog VCC Supply Voltage on Power VCC Voltage at any Input Pins (except Video inputs) and Input/Output Pins Voltage at Video Inputs Storage Temperature Operating Junction Temperature Pin 7 20 1, 3, 5 Value 5.5 8.8 5.5 1.4 +150 Units V V V V C C
6 - THERMAL DATA
Symbol R th(j-a) Tj Parameter Max. Junction-ambient Thermal Resistance Typ. Junction Temperature at Tamb = 25C Value 69 80 Units C/W C
7 - DC ELECTRICAL CHARACTERISTICS
T amb = 25C, VCCA = 5V, VCCP = 8V, unless otherwise specified.
Symbol VCCA VCCP ICCA ICCP VI Vo VIL VIH IIN RHS Parameter Analog Supply Voltage Power Supply Voltage Analog Supply Current Power Supply Current Video Input Voltage Amplitude Output Voltage Range Low Level Input Voltage High Level Input Voltage Input Current Input Resistor OSD, FBLK, BLK, HSYNC 2.4 OSD, FBLK, BLK HSYNC -1 40 1 0.5 Test Conditions Pin 7 Pin 17 VCCA = 5V VCCP = 8V Min. 4.5 4.5 Typ. 5 8 70 55 0.7 1 V CCP -0.5V 0.8 Max. 5.5 8.8 Units V V mA mA V V V V A k
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TDA9210
8 - AC ELECTRICAL CHARACTERISTICS
Tamb = 25C, VCCA = 5V, VCCP= 8V, V i = 0.7 VPP, CLOAD = 5pF RS = 100, serial between output pin and CLOAD, unless otherwise specified.
Symbol Parameter Test Condit ions Min. Typ. Max. Units VIDEO INPUTS (PINS 1, 3, 5) VI GAM VOM VON CAR DAR GM tR, tF BW BW Video Input Voltage Amplitude Maximum Gain Maximum Video Output Voltage (Note 1) Nominal Video Output Voltage Contrast Attenuation Range Drive Attenuation Range Gain Matching Rise Time, Fall Time (Note 2) Large Signal Bandwidth Bandwidth Adjustment Range Max. Contrast and Drive Max Contrast and Drive (CRT = DRV = 254 dec) Max Contrast and Drive (CRT = DRV = 254 dec) Contrast and Drive at POR (CRT = DRV = 180 dec) From max. Contrast (CRT=254 dec) to min. Contrast (CRT = 1 dec) From Max. Drive (DRV = 254 dec) to min Drive (DRV = 1 dec) Contrast and Drive at POR VOUT = 2 VPP (BW = 15 dec) VOUT = 2 VPP (BW = 0 dec) VOUT = 2 V PP VOUT = 2 V PP Minimum bandwidth (BW = 0 dec) Maximum bandwidth (BW =15 dec) VOUT = 2 V PP @ f = 10 MHz @ f = 50 MHz 48
0.1
0.7 16 4.4 2.2 48
1
V dB V V dB dB dB ns ns MHz MHz MHz dB dB V V V mV
VIDEO OUTPUT SIGNAL (PINS 14, 16, 18) - GENERAL
2.7 4.3 130 80 130 60 35 2 0 0.4
CT
Crosstalk between Video Outputs
VIDEO OUTPUT SIGNAL -- BRIGHTNESS BRTmax BRTmin VIP BRTM Maximum Brightness Level Minimum Brightness Level Insertion Pulse Brightness Matching Brightness and Drive at POR Max. Drive (DRV = 254 dec) Max. OSD (OSD = 15 dec) Min. OSD (OSD = 0 dec) Max. Cut-off (Cut-off = 255 dec) Min. Cut-off (Cut-off = 40 dec) Tj variation=100C Max. Brightness (BRT = 255 dec) and Max. Drive (DRV = 254 dec) Min. Brightness (BRT = 0 dec) and Max. Drive (DRV = 254 dec)
10
VIDEO OUTPUT SIGNAL -- OSD OSDmax OSDmin DCLmax DCLmin DCLstep DCLTD Maximum OSD Output Level Minimum OSD Output Level Maximum Output DC Level Minimum Output DC Level Output DC Level Step Output DC Level Drift 4.9 0 2.5 0.4 10 0.5 V V V V mV %
VIDEO OUTPUT SIGNAL -- DC LEVEL (DC COUPLING MODE)
Note 1 : Assuming that VOM remains within the range of Vo (between 0.5V and VCCP - 0.5V) Note 2 : tR, tF are calculated values, assuming an ideal input rise/fall time of 0ns (tR = tROUT2 + tRIN2 , tF = tFOUT2 + tFIN2
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TDA9210
AC ELECTRICAL CHARACTERISTICS
Tamb = 25C, VCCA = 5V, VCCP= 8V, Vi = 0.7 VPP, C LOAD = 5 pF, unless otherwise specified Symbol Parameter Test Condit ions Min. ABL (PIN 2) GABLmin GABLmax VABL IABLhigh IABLlow ABL Mini Attenuation ABL Maxi Attenuation ABL Threshold Voltage High ABL Input Current Low ABL Input Current VABL 3.2 V For output attenuation Typ. Max. Units
VABL = 1 V
0 15 3 0 -2
dB dB V A A
VABL = 3.2V VABL = 1V
9 - I2C ELECTRICAL CHARACTERISTICS
T amb = 25C, VCCA = 5V, unless otherwise specified
Symbol VIL VIH IIN fSCL(Max.) VOL Parameter Low Level Input Voltage High Level Input Voltage Input Current (Pins SDA, SCL) SCL Maximum Clock Frequency Low Level Output Voltage SDA Pin when ACK Sink Current = 6mA 0.4 V < VIN < 4.5 V Test Conditi ons On Pins SDA, SCL 3 -10 200
+10
Min.
Typ.
Max. Units 1.5 V V A kHz V 0.25 0.6
10 - I 2C INTERFACE TIMING REQUIREMENTS
(see Figure 11)
Symbol tBUF tHDS tSUP tLOW tHIGH tHDAT tSUDAT tR, tF Parameter Time the bus must be free between two accesses Hold Time for Start Condition Set-up Time for Stop Condition The Low Period of Clock The High Period of Clock Hold Time Data Set-up Time Data Rise and Fall Time of both SDA and SCL Min. 1300 600 600 1300 600 300 250 20 300 Typ. Max. Units ns ns ns ns ns ns ns ns
Figure 7. I2C Timing Diagram
t SDA t SCL t
HIGH HDS BUF
t
HDAT
t
SUDAT
t
SUP
t
LOW
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TDA9210
11 - I 2C REGISTER DESCRIPTION
Register Sub-addressed - I2C Table 1
Sub-address Hex 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D Dec 01 02 03 04 05 06 07 08 09 10 11 12 13 Contrast (CRT) Brightness (BRT) Drive 1 (DRV) Drive 2 (DRV) Drive 3 (DRV) Not Used OSD Contrast (OSD) BPCP & OCL Miscellaneous Cut Off Out 1 DC Level (Cut-off) Cut Off Out 2 DC Level (Cut-off) Cut Off Out 3 DC Level (Cut-off) Bandwidth Adjustment (BW) 4-bit DAC Refer to the I2C table 2 Refer to the I2C table 3 8-bit DAC 8-bit DAC 8-bit DAC 4-bit DAC 8-bit DAC 8-bit DAC 8-bit DAC 8-bit DAC 8-bit DAC Register Names POR Value Hex B4 B4 B4 B4 B4 09 04 1C B4 B4 B4 07 Dec 180 180 180 180 180 09 04 28 180 180 180 07 FF FF FF 0F 255 255 255 15 Max. Value Hex FE FF FE FE FE 0F Dec 254 255 254 254 254 15
For Contrast & Drive adjustment, code 00 (dec) and 255 (dec) are not allowed. For Output DC Level, code 00(dec), 01(dec), 02(dec) are not allowed (Register 06). For Cut Off Output DC Level, output voltage is linear between code 10 and code 235 (Registers 0A, 0B, 0C).
BPCP & OCL Register (R8) - I2C Table 2 (see also Figure 8)
b7 b6 b5 b4 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 b3 b2 b1 b0 0 1 Function Internal BPCP triggered by HSYNC Internal BPCP triggered by BLK Internal BPCP synchronized by the trailing edge Internal BPCP synchronized by the leading edge Internal BPCP Width = 0.33 s Internal BPCP Width = 0.66 s Internal BPCP Width = 1 s Internal BPCP Width = 1.33 s Internal BPCP = BPCP input (Pin 23) Normal Operation Reserved (Force BPCP to 1 in test) Normal Operation Reserved (Force OCL to 1 in test) Internal OCL pulse triggered by BLK (pin 24) Internal OCL pulse = Internal BPCP x x x x x POR Value x
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TDA9210
Miscellaneous Register (R9) - I2C Table 3
b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 1 x 0 0 0 1 0 1 0 1 0 0 0 1 Function Positive Blanking Polarity Negative Blanking Polarity Soft Blanking = OFF Soft Blanking = ON DC Coupling Mode (Note 3) Light Grey on OSD Outputs = OFF Light Grey on OSD Outputs = ON Dark Grey on OSD Outputs = OFF Dark Grey on OSD Outputs = ON SOG Clipping = OFF SOG Clipping = ON x x x x POR Value x
Note 3 : After Power ON, the DC coupling mode must be programmed in Register 9 by setting bit2=1 and bit3=0.
Bandwidth Adjustment (R13) - I2C Table 4
b7 b6 b5 b4 b3 1 0 0 0 0 1 0 1 0 b2 1 1 0 b1 1 1 0 b0 1 1 0 130 MHz 100 MHz 80 MHz Normal Operation BW DAC output connected to BLK input (for test) BW DAC complementary output connected to BLK input (for test) x x Function POR Value
Figure 8. BPCP and OCL Generation
Source Selection R8b0 HS/BPCP (External) HS edge Selection R8b1 Width Selection R8b2b3 BPCP Source Selection R8b4 BPCP (Internal) Edge Selection Pulse Generation OCL (Internal) Polarity Selection Pulse Generation
23
Automatic Polarity
BLK (External)
24
BLK Polarity Selection R9b0
OCL Source Selection R8b7
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TDA9210
12 - INTERNAL SCHEMATICS
Figure 9.
VCC5 VCCA 30k 7 (8V) LOGIC PART
Figure 12.
IN (Pins 1-3-5)
HIGH IMPEDANCE
GNDA
GNDA 6
Figure 10.
Figure 13.
VCCA OSD-FBLK-HS-BLK Pins 8-9-10 11-19-20 GNDA GNDA GNDL
V CCA 1k ABL 2
Figure 11.
VCCA
Figure 14.
HSYNC 19
GNDL
4
GNDA
GNDA
GNDL
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2
TDA9210
Figure 15.
30k SCL 12 4pF GNDA (8V) GNDL
30k SCA 13 4pF GNDA GNDL
Figure 16.
VCCP
GNDP
15
GNDA
Figure 17.
VCCP 17 OUT Pins 14-16-18 (20V)
GNDA
GNDP
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TDA9210
Figure 18. TDA9210 - TDA9535/9536 Demonstration Board: Silk Screen and Trace (scale 1:1)
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A
B
C
D
E
R20 100R R1 C1(1) 100pF
8V 5V
Hs Out 100R
R18 100R R4 2R7
C3
VsOut
4
5V
4
J1 100nF R2 15R 1 IN1 U2 2 ABL R29 R8 15R 3 IN2 GNDL VCC C6 5 IN3 C24 100nF GND2 6 R17 VDD
5V
D1 R30 BLK 20 FDH400 transientresponse optimisation S_R R6 11 120R
12V
U1 D2(2)
R11 2R7
110V
GRN
5V
1N4148
D3
R3 75R D4 L1 0.33uH 1N4148 C4 100nF OUT1 18 GND3 10 24R 8 C7(1) IN2 R14 47uF 120R R26(2) 39R C10(1) 100nF 250V /
110V
1N4148 C23 OUT3 R9 15R/33R 47pF 7 C8 9 IN3 R31 S_R L2 0.33uH
110V
HS 19
R7
150R
RED D5 C9(1) 100nF 1N4148 100nF OUT2 GNDP 15R/33R 4 R24 GND1 2 24R TDA9535/36 C13 100pF
5V
BLU 4 16 R33 C5(1)100nF 24R 47pF 3 IN1 OUT2 5 C18 4.7uF/ 150V R32 S_R L3 R22 120R R28 J10 10R J5 I2C
110V
12 11 10 9 8 7 6 5 4 3 2 1
110V
R5 75R VCCP 17 R13 15R/33R R12 C22(1) 100nF 6 GNDA VCCA OSD1 R21 2K7 47pF OUT1 1 OSD2 OSD3 TDA9210 1 2 3 4 C12 100pF FBLK 11 SCL 12 SCA 13 R19 2K7 C25 OUT3 14 15 7 8 9 10 15R
5V
D6
D7(2) FDH400 R15 150R
3
Video
5V
1N4148
3
R10 75R R16 2R7
D8
1N4148
D9(2) FDH400 R23 0.33uH Heater 12 GND 11 B 10 H1 H2 R C14 10nF/ 400V 9 8 F1(2) 150R
110V
12V
C17
2
8V
C16 47uF
2
5V
J16
C15 47uF
GND_CRT J7 C21 100nF/ 250V
G2 GND 1 G1
Notes: 1: All capacitorsfollowed by (1) are decoupling capacitors which must be connected as close as possible to the device
7
J8 C19 G1 R27 150R 5 C20 G1 4.7nF/1kV G 6
G2 10nF/ 2KV
F2(2)
1 2 3 4 5 Heater
47uF
J17
Power
Figure 19. TDA9210 - TDA9535/9536 Demonstration Board Schematic
1 2 3 4 5 6 Vs Out
2: The purpose of all components followed by (2) is to ensure a good protectionagainst overvoltage(arcing protection)
F4(2)
Supply Hs Out
1
1
Title
CRT3 with TDA9210 + TDA9535/36
Size Document Number Custom Version 1.4 February 6,2000 1 Date: Wednesday,
B C D
Rev Sheet
E
1
of
1
A
TDA9210
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TDA9210
13 - PACKAGE MECHANICAL DATA
20 Pins -- Plastic Dip
Dimensions a1 B b b1 D E e e3 F I L Z
Millimeters Min. 0.254 1.39 0.45 0.25 25.4 8.5 2.54 22.86 7.1 3.93 3.3 1.34 1.65 Typ. Max. Min. 0.010 0.055
Inches Typ. Max. 0.065 0.018 0.010 1.000 0.335 0.100 0.900 0.280 0.155 0.130 0.053
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TDA9210
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change witho ut notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. (c) 2000 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philip s I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philip s. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www .st.com
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